Complementary Metal Oxide Semiconductor Circuits Research Articles

Performance improvements in complementary metal oxide semiconductor devices and circuits based on fin field-effect transistors using 3-nm ferroelectric Hf0.5Zr0.5O2

AbstractIn this work, a conventional HfO2 gate dielectric layer is replaced with a 3-nm ferroelectric (Fe) HZO layer in the gate stacks of advanced fin field-effect transistors (FinFETs). Fe-induced characteristics, e.g., negative drain induced barrier lowering (N-DIBL) and negative differential resistance (NDR), are clearly observed for both p- and n-type HZO-based FinFETs. These characteristics are attributed to the enhanced ferroelectricity of the 3-nm hafnium zirconium oxide (HZO) film, caused by Al doping from the TiAlC capping layer. This mechanism is verified for capacitors with structures similar to the FinFETs. Owing to the enhanced ferroelectricity and N-DIBL phenomenon, the drain current (IDS) of the HZO-FinFETs is greater than that of HfO2-FinFETs and obtained at a lower operating voltage. Accordingly, circuits based on HZO-FinFET achieve higher performance than those based on HfO2-FinFET at a low voltage drain (VDD), which indicates the application feasibility of the HZO-FinFETs in the ultra-low power integrated circuits. Graphical abstract

Exploring Terahertz COMPLEMENTARY METAL OXIDE SEMICONDUCTOR Integrated Circuits: Advancements and Obstacles

The text provides a description of the characteristics of several NMOS and CMOS circuit approaches, as well as an explanation of the limitations associated with each technology. Next, the CMOS domino circuit, a novel form of circuit, is explained. This entails interconnecting dynamic CMOS gates in a manner that enables the activation of all gates in the circuit simultaneously using a single clock edge. Consequently, there is no need for intricate clocking methods, allowing the dynamic gate to operate at its maximum speed. This circuit features a basic mode voltage-controlled oscillator operating at 135 GHz in 80-nm COMPLEMENTARY METAL OXIDE SEMICONDUCTOR, a 405 GHz push-push voltage controller in 38-nm COMPLEMENTARY METAL OXIDE SEMICONDUCTOR with an on-chip patch antenna, a 128 GHz Schottky diode frequency doubler, a 170 GHz Schottky diode detector, a 600 GHz plasma wave detector in 122-nm COMPLEMENTARY METAL OXIDE SEMICONDUCTOR and a 40 GHz phase-locked loop with a frequency doubled output at 110 GHz. Given this and the trends in performance of n METAL OXIDE SEMICONDUCTOR transistors and Schottky diodes produced in complementary metal-oxide semiconductors, we lay out a plan for terahertz COMPLEMENTARY METAL OXIDE SEMICONDUCTOR systems and circuits, highlighting critical challenges that need to be addressed. With the advent of terahertz COMPLEMENTARY METAL OXIDE SEMICONDUCTOR

CMOS plus stochastic nanomagnets enabling heterogeneous computers for probabilistic inference and learning

Extending Moore’s law by augmenting complementary-metal-oxide semiconductor (CMOS) transistors with emerging nanotechnologies (X) has become increasingly important. One important class of problems involve sampling-based Monte Carlo algorithms used in probabilistic machine learning, optimization, and quantum simulation. Here, we combine stochastic magnetic tunnel junction (sMTJ)-based probabilistic bits (p-bits) with Field Programmable Gate Arrays (FPGA) to create an energy-efficient CMOS + X (X = sMTJ) prototype. This setup shows how asynchronously driven CMOS circuits controlled by sMTJs can perform probabilistic inference and learning by leveraging the algorithmic update-order-invariance of Gibbs sampling. We show how the stochasticity of sMTJs can augment low-quality random number generators (RNG). Detailed transistor-level comparisons reveal that sMTJ-based p-bits can replace up to 10,000 CMOS transistors while dissipating two orders of magnitude less energy. Integrated versions of our approach can advance probabilistic computing involving deep Boltzmann machines and other energy-based learning algorithms with extremely high throughput and energy efficiency.

Ultra-fast switching memristors based on two-dimensional materials

The ability to scale two-dimensional (2D) material thickness down to a single monolayer presents a promising opportunity to realize high-speed energy-efficient memristors. Here, we report an ultra-fast memristor fabricated using atomically thin sheets of 2D hexagonal Boron Nitride, exhibiting the shortest observed switching speed (120 ps) among 2D memristors and low switching energy (2pJ). Furthermore, we study the switching dynamics of these memristors using ultra-short (120ps-3ns) voltage pulses, a frequency range that is highly relevant in the context of modern complementary metal oxide semiconductor (CMOS) circuits. We employ statistical analysis of transient characteristics to gain insights into the memristor switching mechanism. Cycling endurance data confirms the ultra-fast switching capability of these memristors, making them attractive for next generation computing, storage, and Radio-Frequency (RF) circuit applications.

In-sensor nonlinear convolutional processing based on hybrid MTJ/CMOS arrays

In-sensor computing implemented by novel neuromorphic devices has been regarded as the potential technology to break the acquisition wall. Moreover, the nonlinear convolution inspired by the biological neural system outperforms the traditional linear convolution. Therefore, realizing the in-sensor nonlinear convolutional processing with the intrinsic nonlinearity of novel neuromorphic devices would be exciting and hardware friendly. Here, a new type of in-sensor nonlinear convolutional processing architecture is proposed based on STT-MTJ (spin transfer torque-magnetic tunnel junction) devices and simple peripheral circuits. The nonlinear dynamic characters of the STT-MTJ device are regulated by bias currents and magnetic fields. Meanwhile, the hybrid STT-MTJ/CMOS (complementary metal oxide semiconductor) circuit exhibits nonlinear dependence of the output voltage on bias currents and magnetic fields. In this way, a nonlinear convolutional unit is developed by the inherent property of hardware. Based on the in-sensor nonlinear convolutional unit, a convolutional network is simulated to perform the classification task, and a high accuracy is realized. This work indicates that the in-sensor nonlinear convolution offers a promising way to develop in-sensor computing at the edge intelligence devices.

Three-dimensional sensing of surfaces by projection of invisible electroluminescence from organic light-emitting diodes.

Organic light-emitting diodes (OLEDs) that efficiently emit near-infrared (NIR) light and consume little power will create valuable applications for OLEDs beyond just displays. Here, we report such a NIR-OLED with high operational stability that can be used as a light source for three-dimensional sensing of object's surfaces. Using a narrow-energy-gap material as a host for producing NIR hyperfluorescence system, we fabricated a NIR-OLED exhibiting intense emission at 930 nm with a high external electroluminescence quantum efficiency of more than 1% at a current density of 100 milliamperes per square meter without any degradation even after more than 300 hours of operation. The NIR-OLEDs were integrated with dense complementary metal-oxide semiconductor circuits to make a micro-NIR-OLED projector (0.21 inch, 230,400 pixels). By actively driving the projector on a pixel by pixel and projecting their emission onto objects, we successfully scanned and sensed the surfaces in three dimensions with invisible NIR.

Ultra-low-power CMOS ring oscillator with minimum power consumption of 2.9 pW using low-voltage biasing technique

Abstract The need for low-power low-voltage circuit so lutions increases significantly with the rapid spread of wireless sensor network (WSN) and energy harvesting applications. The design of Complementary Metal-Oxide Semiconductor (CMOS) oscillators in sub-threshold region is challenged by the limits of the minimum start-up sup ply voltage, the power available from the harvester, die area, the demand of fully integrated CMOS circuits, and the additional auxiliary circuits that are needed to stabilize the frequency vs a supply voltage V DD. In this work, low-power CMOS oscillator with a simplified design is proposed in order to overcome the aforementioned obstacles. The circuit is designed using 2.5 µm 2-polySi 2-metal CMOS technology from IMB–CNM (CSIC) [1] with a threshold voltage of n-channel metal oxide semiconductor NMOS and p-channel metal oxide semiconductor PMOS transistors of 0.86 and −1.52 V, respectively. The suggested oscillator is capable to start up even in the deep sub-threshold region at V DD of 0.25 V. Accordingly, the minimum power consumption is 2.9 pW with an oscillation frequency of 2 Hz. The circuit can produce a P–P voltage of the oscillation signal equal to the supply voltage within a power supply range of 0.25–1.25 V.

Hierarchies in Visual Pathway: Functions and Inspired Artificial Vision.

The development of artificial intelligence has posed a challenge to machine vision based on conventional complementary metal-oxide semiconductor (CMOS) circuits owing to its high latency and inefficient power consumption originating from the data shuffling between memory and computation units. Gaining more insights into the function of every part of the visual pathway for visual perception can bring the capabilities of machine vision in terms of robustness and generality. Hardware acceleration of more energy-efficient and biorealistic artificial vision highly necessitates neuromorphic devices and circuits that are able to mimic the function of each part of the visual pathway. In this paper, wereview the structure and function of the entire class of visual neurons from the retina to the primate visual cortex within reach (Chapter 2) are reviewed. Based on the extraction of biological principles, the recent hardware-implemented visual neurons located in different parts of the visual pathway are discussed in detail in Chapters 3 and 4. Furthermore, valuable applications of inspired artificial vision in different scenarios (Chapter 5) are provided. The functional description of the visual pathway and its inspired neuromorphic devices/circuits are expected to provide valuable insights for the design of next-generation artificial visual perception systems.

Monolithic 3D Integration of Analog RRAM-based Computing-in-Memory and Sensor for Energy-Efficient Near-Sensor Computing.

In the era of the Internet of Things, vast amounts of data generated at numerous sensory nodes impose critical challenges on the data-transfer bandwidth and energy efficiency of computing hardware. A near-sensor computing (NSC) architecture places the processing units closer to the sensors such that the generated data can be processed almost in situ with high efficiency. This study demonstrates the monolithic three-dimensional (M3D) integration of a photosensor array, analog computing-in-memory (CIM), and Si complementary metal-oxide-semiconductor (CMOS) logic circuits, named M3D-SAIL. This approach exploits the high-bandwidth on-chip data transfer and massively parallel CIM cores to realize an energy-efficient NSC architecture. The 1st layer of the Si CMOS circuits served as the control logic and peripheral circuits. The 2nd layer comprised a 1k-bit one-transistor-one-resistor (1T1R) array with InGaZnOx field-effect transistor (IGZO-FET) and resistive random-access memory (RRAM) for analog CIM. The 3rd layer comprised multiple IGZO-FET-based photosensor arrays for wavelength-dependent optical sensing. The structural integrity and function of each layer were comprehensively verified. Furthermore, NSC was implemented using the M3D-SAIL architecture for a typical video keyframe-extraction task, achieving a high classification accuracy of 96.7% as well as a 31.5× lower energy consumption and 1.91× faster computing speed compared to its 2D counterpart. This article is protected by copyright. All rights reserved.

Matched printed carbon nanotube complementary metal-oxide-semiconductor (CMOS) devices for flexible circuits

The development of matched carbon nanotube (CNT) complementary metal-oxide-semiconductor (CMOS) devices still remains a challenge for flexible and low-power-dissipation circuits. In this study, we found a reliable technique to achieve matched CNT CMOS thin-film transistors (TFTs) for integrated circuits (IC) with low power consumption. The enhancement-mode p-type CNT TFTs were obtained using the low-work-function Al gate electrodes and ultrathin (10 nm) Al2O3 dielectrics, which exhibit the average field-effect mobility(μ) of 6.5 cm2V−1s−1, subthreshold swing (SS) down to 70–85 mV/dec and on/off ratio up to 106 at the low working voltages between −1.5 V and 0.5 V, as well the outstanding stability and mechanical flexibility after 10,000 cycles of bending. Then, by adjusting the aspect ratios of the TFT channels and selectively dropping the electron-doping inks into p-type CNT TFTs’ channels, matched n-type and p-type CNT TFTs were obtained. Finally, flexible printed CMOS inverters with high noise tolerance (84% of 1/2 VDD), high voltage gain (over 32), and low power consumption (down to 32.9 pW) were successfully constructed, owing to the work style of CMOS circuits and electrically symmetrical n-type and p-type TFTs. Furthermore, good-performance NAND and NOR gates have been demonstrated. This work can effectively resolve the leakage current issue of flexible carbon-based electronics with the ultra-thin dielectrics by optimizing the conductive ink formula and printing technology.

Room temperature-grown highly oriented p-type nanocrystalline tellurium thin-films transistors for large-scale CMOS circuits

Although facile fabrication of high-performance thin-film transistor (TFT)-based complementary metal oxide–semiconductor (CMOS) circuits over a large area has generated significant interest, the lack of reliable and uniform p-type TFTs is hindering it. In this study, we prepared high-performance CMOS circuits using room temperature deposited nanocrystalline tellurium (nc-Te) and sputtered amorphous-indium gallium zinc oxide (a-IGZO) TFTs. The facile polyethyleneimine (PEI) surface treatment enabled Te atom anchoring and crystal orientation control along with continuous surface coverage, resulting in a high-performance TFT with an average mobility of 21.1 cm2V−1s−1 and an Ion/Ioff ratio of 104. By introducing monolithic integration of nc-Te and a-IGZO TFTs, various CMOS circuits including inverter, NAND, and NOR circuits were fabricated and operated quite logically. Moreover, seven-stage ring oscillators comprising 14 cross-wired TFTs validated the cascading of multiple stages and device uniformity of the complementary system, achieving an oscillation frequency up to 392.16 kHz at VDD of 20 V. nc-Te on a PEI-treated surface offers a general route to producing high-performance and stable p-type semiconductors while ensuring compatibility with standard CMOS processing and large-scale on-chip device applications.

Python-Based Circuit Design for Fundamental Building Blocks of Spiking Neural Network

Spiking neural networks (SNNs) are considered a crucial research direction to address the “storage wall” and “power wall” challenges faced by traditional artificial intelligence computing. However, developing SNN chips based on CMOS (complementary metal oxide semiconductor) circuits remains a challenge. Although memristor process technology is the best alternative to synapses, it is still undergoing refinement. In this study, a novel approach is proposed that employs tools to automatically generate HDL (hardware description language) code for constructing neuron and memristor circuits after using Python to describe the neuron and memristor models. Based on this approach, HR (Hindmash–Rose), LIF (leaky integrate-and-fire), and IZ (Izhikevich) neuron circuits, as well as HP, EG (enhanced generalized), and TB (the behavioral threshold bipolar) memristor circuits are designed to construct the most basic connection of a SNN: the neuron–memristor–neuron circuit that satisfies the STDP (spike-timing-dependent-plasticity) learning rule. Through simulation experiments and FPGA (field programmable gate array) prototype verification, it is confirmed that the IZ and LIF circuits are suitable as neurons in SNNs, while the X variables of the EG memristor model serve as characteristic synaptic weights. The EG memristor circuits best satisfy the STDP learning rule and are suitable as synapses in SNNs. In comparison to previous works on hardware spiking neurons, the proposed method needed fewer area resources for creating spiking neurons models on FPGA. The proposed SNN basic components design method, and the resulting circuits, are beneficial for architectural exploration and hardware–software co-design of SNN chips.

Low-thermal-budget synthesis of monolayer molybdenum disulfide for silicon back-end-of-line integration on a 200 mm platform.

Two-dimensional (2D) materials are promising candidates for future electronics due to their excellent electrical and photonic properties. Although promising results on the wafer-scale synthesis (≤150 mm diameter) of monolayer molybdenum disulfide (MoS2) have already been reported, the high-quality synthesis of 2D materials on wafers of 200 mm or larger, which are typically used in commercial silicon foundries, remains difficult. The back-end-of-line (BEOL) integration of directly grown 2D materials on silicon complementary metal-oxide-semiconductor (CMOS) circuits is also unavailable due to the high thermal budget required, which far exceeds the limits of silicon BEOL integration (<400 °C). This high temperature forces the use of challenging transfer processes, which tend to introduce defects and contamination to both the 2D materials and the BEOL circuits. Here we report a low-thermal-budget synthesis method (growth temperature < 300 °C, growth time ≤ 60 min) for monolayer MoS2 films, which enables the 2D material to be synthesized at a temperature below the precursor decomposition temperature and grown directly on silicon CMOS circuits without requiring any transfer process. We designed a metal-organic chemical vapour deposition reactor to separate the low-temperature growth region from the high-temperature chalcogenide-precursor-decomposition region. We obtain monolayer MoS2 with electrical uniformity on 200 mm wafers, as well as a high material quality with an electron mobility of ~35.9 cm2 V-1 s-1. Finally, we demonstrate a silicon-CMOS-compatible BEOL fabrication process flow for MoS2 transistors; the performance of these silicon devices shows negligible degradation (current variation < 0.5%, threshold voltage shift < 20 mV). We believe that this is an important step towards monolithic 3D integration for future electronics.

Recent progress of the p-type oxide thin films for transistor applications: Nickel oxide, Tin oxide, and Copper oxide

Over the past decade, many research groups have been striving to develop high-performance p-type switching oxide materials for implementing complementary metal–oxide–semiconductor (CMOS) thin film devices. However, realizing p-type oxide thin film transistors (TFTs) whose electrical properties are comparable to n-type oxide TFTs has been challenging. This is because of inherent characteristics of p-type oxide materials such as the high formation energy of native acceptors and high hole effective mass caused by localized hole transport path. Developing a p-type oxide with a delocalized hole transport pathway and low hole formation energy is crucial for the production of CMOS circuits utilizing oxide thin films. NiO, SnO, and CuO&lt;sub&gt;x&lt;/sub&gt; are being actively studied as candidate materials that satisfy these requirements. This review discusses the latest advances in the synthesis method of p-type binary oxide thin films and the approach for electrical performance enhancement.

Fully-Solution-Processed Enhancement-Mode Complementary Metal-Oxide-Semiconductor Carbon Nanotube Thin Film Transistors Based on BiI3 -Doped Crosslinked Poly(4-Vinylphenol) Dielectrics for Ultralow-Power Flexible Electronics.

The threshold voltage (Vth ) adjustment of complementary metal-oxide-semiconductor (CMOS) thin film transistors (TFTs) is one of the research hotspotsdue to its key role in energy consumption control of CMOS circuits. Here, ultralow-power flexible CMOS circuits based on well-matched enhancement-mode (E-mode) CMOS single-walled carbon nanotube (SWCNT) TFTs are successfully achieved through tuning the work function of gate electrodes, electron doping, and printing techniques. E-mode P-type CMOS SWCNT TFTs with the full-solution procedure are first obtained through decreasing the work function ofAg gate electrodes directly caused by the deposition of bismuth iodide(BiI3 )-doped solid-state electrolyte dielectrics. After synthetic optimization of dielectric compositions and semiconductor printing process, the flexible printed E-mode SWCNT TFTs show the high Ion /Ioff ratios of ≈106 , small subthreshold swing (SS) of 70-85mV dec-1 ,lowoperating voltages of ≈0.5 to -1.5V, good stabilityand excellent mechanical flexibility during 10000 bending cycles. E-mode N-type SWCNT TFTs are then selectively achieved via printing the polarity conversion ink (2-Amino-2-methyl-1-propanol (AMP) aselectron dopingagent) in P- type TFT channels. Last, printed SWCNT CMOS invertersare successfully constructed with full rail-to-rail output characteristics and the record unit static power consumption of 6.75 fW µm-1 at VDD of 0.2V.

High-performance broadband graphene/silicon/graphene photodetectors: From x-ray to near-infrared

Metal–semiconductor–metal (MSM) structures have been widely used and extensively investigated for ultraviolet (UV) detection. However, traditional MSM structures suffer from large dark currents, narrow detection bands, and low collection efficiency. Optimizing these properties for broadband detection in MSM structures is essential for improving the performance and functionality in broader optoelectronics applications. We report a high-performance broadband graphene/thin silicon/graphene photodetector by realizing a synergistic combination of graphene and silicon absorption bandwidths from the x-ray to near-infrared regions. The sensitivity of the proposed photodetector in this spectral range is greatly enhanced. A high responsivity of 0.56 A/W, a high detectivity of 2.72 × 1011 Jones, and a fast response time of 7.2 ns are achieved. Moreover, the real-time array imaging at broadband regions presented in this study can benefit from the independent pixel structures similar to the complementary-metal-oxide-semiconductor (CMOS) architecture. This approach constitutes a reliable route toward a high-performance photodetector with prominent broad-spectrum response, high responsivity, and low noise. These results will motivate strategies to achieve high-performance, broadband image sensors, compatible for on-chip CMOS circuit technology that advances the development of next-generation graphene/silicon image sensors.

Low-temperature solution-processed nanoparticle-doped nickel oxide thin-film transistor

Developing p-type oxide thin-film transistors (TFTs) is an essential path for further application in complementary metal oxide semiconductor (CMOS) components. However, the inferior electrical performance of p-type MO TFTs compared to n-type TFTs remains an ongoing challenge. Herein, for the first time, a low temperature, facile material engineering approach by incorporating n-type nanoparticles (NPs) was proposed for preparing p-type transparent NiOx TFTs. The characteristics of thin films blending NPs and the electrical performances of TFTs were investigated. The field effect mobility of TFTs with doping was nearly 20 times higher than pristine TFTs without doping, which was mainly beneficial from the suitable band alignment between NPs and p-type oxide, the increasing Ni3+ oxidation state in NiOx, as well as the improved dielectric/semiconductor interface quality. Electrons from drain electrode injected into metal oxide turn accepted in NPs rather than being trapped in the dielectric/semiconductor interface due to a strong surface electron depletion effect of NPs. NPs with small particle size and appropriate concentration would promote continuous hole transport by electrons transferring and reducing the interface trap state. The facile material engineering strategy is a promising technique for preparing p-type transparent MO-TFTs at low temperature, which showed great potential to be applicable in CMOS circuits on flexible substrates.

Performance analysis of CMOS based analog circuit design with PVR variation

Process, supply voltage, and temperature (PVT) are three important factors which contribute to performance variation of the complementary metal–oxide–semiconductor (CMOS) based analog circuits. In this paper, CMOS based analog circuit design with the PVT variation effects are explored. The effects of the PVT variation on the performance of CMOS based analog circuits are introduced. The optimization of CMOS based analog circuits such as differential amplifier (DA) and two-stage operational amplifier (op amp) circuits with PVT variations with different algorithms such as cockoo search (CS), particle swam optimization (PSO), hybrid CSPSO, and differential evaluation (DE) algorithms is presented. Each algorithm is implemented using the C programming language, interfaced with Ngspice circuit simulator, and tested on the Intel®core™ i5, 2.40 GHz processor with 8 GB internal RAM using the Ubuntu operating system (OS). The result shows PVT variation affects the performance of CMOS circuit.

A nanomagnets majority logic gate based on heterogeneous multiferroic structure global strain clock

&lt;sec&gt;In the post-Moore era, nanomagnetic logic circuits have shown great potential to replace complementary metal oxide semiconductor (CMOS) circuits. A majority logic gate, as the core of a nanomagnetic logic circuit, is equivalent to the inverter in the CMOS circuit. A nanomagnetic logic majority gate generally has four nanomagnets arranged in a “T” shape. The nanomagnets in the three corners of the “T” (&lt;i&gt;I&lt;/i&gt;&lt;sub&gt;1&lt;/sub&gt;, &lt;i&gt;I&lt;/i&gt;&lt;sub&gt;2&lt;/sub&gt;, &lt;i&gt;I&lt;/i&gt;&lt;sub&gt;3&lt;/sub&gt;) are the three inputs, and the middle nanomagnet is the output (&lt;i&gt;O&lt;/i&gt;).&lt;/sec&gt;&lt;sec&gt;This paper proposes a nanomagnet majority logic gate based on the global strain clock of heterogeneous multiferroic structure, by utilizing the difference in response to the same strain between positive magnetostrictive coefficient material (Terfenol-D) and negative magnetostrictive coefficient material (Ni). From bottom to top, the device is mainly composed of a silicon substrate, a piezoelectric layer, and four elliptical cylindrical nanomagnets. PMN-PT is used as the piezoelectric layer’s material, and three Ni-based nanomagnets (&lt;i&gt;I&lt;/i&gt;&lt;sub&gt;1&lt;/sub&gt;, &lt;i&gt;I&lt;/i&gt;&lt;sub&gt;2&lt;/sub&gt;, and &lt;i&gt;I&lt;/i&gt;&lt;sub&gt;3&lt;/sub&gt;) are utilized as input, while Terfenol-D is used as the material for the output nanomagnet (&lt;i&gt;O)&lt;/i&gt;.&lt;/sec&gt;&lt;sec&gt;Besides, a two-step calculation mode of “high-stress start-low-stress calculation” is designed, that is, the &lt;i&gt;O&lt;/i&gt; is first switched to the “Null” with a stress of –30 MPa, and then the stress decreases to –15 MPa, so that the &lt;i&gt;O&lt;/i&gt; can realize majority calculation under the coupling of &lt;i&gt;I&lt;/i&gt;&lt;sub&gt;1&lt;/sub&gt;, &lt;i&gt;I&lt;/i&gt;&lt;sub&gt;2&lt;/sub&gt;, and &lt;i&gt;I&lt;/i&gt;&lt;sub&gt;3&lt;/sub&gt;. The micromagnetic simulation software MuMax3 is adopted to simulate the performance of the device. The results reveal that the device can successfully perform continuous majority calculation through any three-terminal input combination. By using the two-step calculation mode, the calculation accuracy of the device can reach 100%, its cycle of continuous calculation is 2.75 ns, and the cycle energy consumption is about 64 aJ. It is found that the change of energy potential well, caused by the change of stress anisotropy energy and dipole coupling energy, is the main reason that determines the magnetization dynamic behavior of the device. Therefore, the results of this paper can provide important guidance for designing nanomagnetic logic circuits.&lt;/sec&gt;

An Optimal DPM Based Energy-Aware Task Scheduling for Performance Enhancement in Embedded MPSoC

Minimizing the energy consumption to increase the life span and performance of multiprocessor system on chip (MPSoC) has become an integral chip design issue for multiprocessor systems. The performance measurement of computational systems is changing with the advancement in technology. Due to shrinking and smaller chip size power densities on-chip are increasing rapidly that increasing chip temperature in multi-core embedded technologies. The operating speed of the device decreases when power consumption reaches a threshold that causes a delay in complementary metal oxide semiconductor (CMOS) circuits because high on-chip temperature adversely affects the life span of the chip. In this paper an energy-aware dynamic power management technique based on energy aware earliest deadline first (EA-EDF) scheduling is proposed for improving the performance and reliability by reducing energy and power consumption in the system on chip (SOC). Dynamic power management (DPM) enables MPSOC to reduce power and energy consumption by adopting a suitable core configuration for task migration. Task migration avoids peak temperature values in the multi-core system. High utilization factor ( on central processing unit (CPU) core consumes more energy and increases the temperature on-chip. Our technique switches the core by migrating such task to a core that has less temperature and is in a low power state. The proposed EA-EDF scheduling technique migrates load on different cores to attain stability in temperature among multiple cores of the CPU and optimized the duration of the idle and sleep periods to enable the low-temperature core. The effectiveness of the EA-EDF approach reduces the utilization and energy consumption compared to other existing methods and works. The simulation results show the improvement in performance by optimizing 4.8% on 9%, 16%, 23% and 25% at 520 MHz operating frequency as compared to other energy-aware techniques for MPSoCs when the least number of tasks is in running state and can schedule more tasks to make an energy-efficient processor by controlling and managing the energy consumption of MPSoC.